Congratulations to last year's winners!

Congratulations to the winning team from Glendale Community College.

Student Team Members: John Buhanan, Anthony Christie, Vladimir Frisby

Faculty Coach: Paula Cheslik

The winning team is seen here with Steve Phillips, Chief Information Officer for Avnet, Inc.

Teams will design and demonstrate a digital design to achieve a specific set of criteria revealed at the starting time. Students will demonstrate their work, and write and present a technical presentation.

2-3 students per team

maximum of 6 teams; 1 per college

Registration Deadline:

March 2, 2010 – Registration is closed.

Disciplines / Skills Recommended:

• This event is limited to students taking “Intro to Digital Design” in the current academic year (Fall ’09 or Spring ’10).
• Electrical, Computer Science and Computer System engineering, Electronics and Manufacturing disciplines.
• Familiarity with Digital Logic Design, Xilinx ISE software and an FPGA Development Board

Event Description:

Students will have 4 hours to create, validate, and document an FPGA design that works on the provided circuit board.

This may require that you:

• Develop a block diagram of the design
• Determine a timing control algorithm, create timing diagrams
• Develop state diagrams and truth tables
• Perform mathematical analysis
• Create schematics
• Write code in VHDL or Verilog
• Create design constraints files
• Perform logic simulation and timing analysis

Schedule:

• 7:30 a.m. - Breakfast available
• 8:00 a.m. - 12:00 p.m. - Complete the design challenge
• 11:30 a.m. - 1:00 p.m. - On-the-go lunch
• 12:00 p.m. (NOON) - Event complete; All projects are due at 12 sharp.
• 12:00 - 12:30 p.m. - Pre-judging if necessary
• 12:30 - 3:00 p.m. - Judging (time slots randomly assigned)
• 3:00 - 4:00 p.m. - Networking Hour
• 4:00 - 5:00 p.m. - Awards Reception

Equipment Requirements for Avnet:

• Avnet will provide laptops preloaded with Xilinx ISE software and PowerPoint.
• Avnet will provide FPGA development boards with documentation and additional hardware and IP as needed for the design.
• Avnet will provide a USB memory stick for each team to turn in their design and presentation.
• No other student resources are required or allowed.

Grading Summary (100 pts total)

• 25 pts - Demonstration of a working design
• 25 pts - Design process: synthesis of ideas, problem breakdown, design methods
• 25 pts - Implementation: accuracy and efficiency of actual design, readability
• 25 pts - Team Presentation

The following is an example design challenge (from ATG2009):

Your Task: You are to design a 60-second clock which displays the current time in seconds on a two-digit seven-segment display. Your clock should operate as follows:

• Upon reset (RESET pushbutton) the clock should display "00" and begin counting.
• The clock shall run continuously, changing on one second intervals unless manually paused or reset.
• The count shall be displayed in decimal format.
• While a finger is held on the PUSH_A button, the clock shall pause with its current value, and then continue counting with the next value when the finger is removed.

Additional considerations:

• You may use any of the board's clock sources so long as the displayed clock counts in one second intervals. You will be asked to demonstrate the accuracy of your clock.
• You may implement your design with VHDL, Verilog or schematics. There will be no penalty for the methodology used.
• You will demonstrate and give a 20-minute presentation on your design.
• At the official deadline, you must turn in your presentation and FPGA programming file on a USB memory stick which will be returned to you at the time of your presentation. The presentation room will have an identical laptop and set of hardware.

FAQs:

For more information, e-mail AvnetTechGames@Avnet.com or call (480) 643-7657.

Scholarships and honorariums provided by Carstens Family Funds and administered by the Arizona Technology Council.